A scalable neural chip with synaptic electronics using CMOS integrated memristors.

01:55 EST 28th February 2015 | BioPortfolio

Summary of "A scalable neural chip with synaptic electronics using CMOS integrated memristors."

The design and simulation of a scalable neural chip with synaptic electronics using nanoscale memristors fully integrated with complementary metal-oxide-semiconductor (CMOS) is presented. The circuit consists of integrate-and-fire neurons and synapses with spike-timing dependent plasticity (STDP). The synaptic conductance values can be stored in memristors with eight levels, and the topology of connections between neurons is reconfigurable. The circuit has been designed using a 90 nm CMOS process with via connections to on-chip post-processed memristor arrays. The design has about 16 million CMOS transistors and 73 728 integrated memristors. We provide circuit level simulations of the entire chip performing neuronal and synaptic computations that result in biologically realistic functional behavior.

Affiliation

HRL Laboratories LLC, Malibu, CA 90265, USA.

Journal Details

This article was published in the following journal.

Name: Nanotechnology
ISSN: 1361-6528
Pages: 384011

Links

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Medical and Biotech [MESH] Definitions

The communication from a NEURON to a target (neuron, muscle, or secretory cell) across a SYNAPSE. In chemical synaptic transmission, the presynaptic neuron releases a NEUROTRANSMITTER that diffuses across the synaptic cleft and binds to specific synaptic receptors, activating them. The activated receptors modulate specific ion channels and/or second-messenger systems in the postsynaptic cell. In electrical synaptic transmission, electrical signals are communicated as an ionic current flow across ELECTRICAL SYNAPSES.

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