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Hierarchical Temporal Memory (HTM) is an online machine learning algorithm that emulates the neo-cortex. The development of a scalable on-chip HTM architecture is an open research area. The two core substructures of HTM are spatial pooler and temporal memory. In this work, we propose a new Spatial Pooler circuit design with parallel memristive crossbar arrays for the 2D columns. The proposed design was validated on two different benchmark datasets, face recognition, and speech recognition. The circuits are simulated and analyzed using a practical memristor device model and 0.18 μm IBM CMOS technology model. The databases AR, YALE, ORL, and UFI, are used to test the performance of the design in face recognition. TIMIT dataset is used for the speech recognition.
This article was published in the following journal.
Name: IEEE transactions on biomedical circuits and systems
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Memristor describes the relationship between charge and flux. Although several window functions for memristors based on the HP linear and nonlinear dopant drift models have been studied, most of them ...
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Methods used to take into account and incorporate spatial autocorrelation and regional variation into regression analysis models of data that has spatial dependency, and also to provide information on the spatial relationships among the variables.
Integration of spatial information perceived by visual and/or auditory CUES.
A process through which individuals encode information about their environmental CUES to facilitate SPATIAL NAVIGATION.
Memory related to spatial information.
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