A Power and Area Efficient CMOS Stochastic Neuron for Neural Networks Employing Resistive Crossbar Array.

08:00 EDT 4th October 2019 | BioPortfolio

Summary of "A Power and Area Efficient CMOS Stochastic Neuron for Neural Networks Employing Resistive Crossbar Array."

A power and area efficient CMOS stochastic neuron for resistive computing device-based neural networks is presented. The stochastic neuron performs both quantization and activation function simultaneously by using a single dynamic comparator and allows power-hungry analog to digital and digital to analog converters to be removed at the cost of the increased computation time. A network learning method utilizing a noisy sigmoid function is also presented to minimize the computation time with little accuracy degradation. A prototype neuron chip fabricated in 0.18μm CMOS process successfully demonstrates the neuron's performance and the learning method is verified through network simulations.


Journal Details

This article was published in the following journal.

Name: IEEE transactions on biomedical circuits and systems
ISSN: 1940-9990


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